? semiconductor components industries, llc, 2011 august, 2011 ? rev. 6 1 publication order number: ntd18n06l/d ntd18n06l, NTDV18N06L power mosfet 18 a, 60 v, logic level n ? channel dpak designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. features ? aec q101 qualified ? NTDV18N06L ? these devices are pb ? free and are rohs compliant typical applications ? power supplies ? converters ? power motor controls ? bridge circuits maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 60 vdc drain ? to ? gate voltage (r gs = 10 m ) v dgr 60 vdc gate ? to ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gs 15 20 vdc drain current ? continuous @ t a = 25 c ? continuous @ t a = 100 c ? single pulse (t p 10 s) i d i d i dm 18 10 54 adc apk total power dissipation @ t a = 25 c derate above 25 c total power dissipation @ t a = 25 c (note 2) p d 55 0.36 2.1 w w/ c w operating and storage temperature range t j , t stg ? 55 to +175 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 50 vdc, v gs = 5.0 vdc, l = 1.0 mh, i l (pk) = 12 a, v ds = 60 vdc) e as 72 mj thermal resistance ? junction ? to ? case ? junction ? to ? ambient (note 1) ? junction ? to ? ambient (note 2) r jc r ja r ja 2.73 100 71.4 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommen- ded operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. when surface mounted to an fr ? 4 board using the minimum recommended pad size. 2. when surface mounted to an fr ? 4 board using the 0.5 sq in drain pad size. n ? channel d s g 60 v 54 m 5.0 v r ds(on) typ 18 a (note 1) i d max v (br)dss see detailed ordering and shipping information in the package dimensions section on p age 2 of this data sheet. ordering information 18n6l = device code y = year ww = work week g = pb ? free device 1 gate 3 source 2 drain 4 drain dpak case 369c style 2 marking diagrams 1 2 3 4 1 gate 3 source 2 drain 4 drain dpak ? 3 case 369d style 2 1 2 3 4 yww 18 n6lg http://onsemi.com yww 18 n6lg
ntd18n06l, NTDV18N06L http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (note 3) (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 60 ? 70 57.6 ? ? vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? ? ? 1.0 10 adc gate ? body leakage current (v gs = 15 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.8 5.2 2.0 ? vdc mv/ c static drain ? to ? source on ? resistance (note 3) (v gs = 5.0 vdc, i d = 9.0 adc) r ds(on) ? 54 65 m static drain ? to ? source on ? resistance (note 3) (v gs = 5.0 vdc, i d = 18 adc) (v gs = 5.0 vdc, i d = 9.0 adc, t j = 150 c) v ds(on) ? ? 1.0 0.86 1.3 ? vdc forward transconductance (note 3) (v ds = 7.0 vdc, i d = 9.0 adc) g fs ? 13.5 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 482 675 pf output capacitance c oss ? 166 230 transfer capacitance c rss ? 56 80 switching characteristics (note 4) turn ? on delay time (v dd = 30 vdc, i d = 18 adc, v gs = 5.0 vdc, r g = 9.1 ) (note 3) t d(on) ? 9.9 20 ns rise time t r ? 79 160 turn ? off delay time t d(off) ? 19 40 fall time t f ? 38 80 gate charge (v ds = 48 vdc, i d = 18 adc, v gs = 5.0 vdc) (note 3) q t ? 11 22 nc q 1 ? 3.2 ? q 2 ? 6.5 ? source ? drain diode characteristics forward on ? voltage (i s = 18 adc, v gs = 0 vdc) (note 3) (i s = 18 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? 0.94 0.83 1.15 ? vdc reverse recovery time (i s = 18 adc, v gs = 0 vdc, di s /dt = 100 a/ s) (note 3) t rr ? 41 ? ns t a ? 26 ? t b ? 15 ? reverse recovery stored charge q rr ? 0.057 ? c 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures. ordering information device package shipping ? ntd18n06lt4g dpak (pb ? free) 2500 / tape & reel NTDV18N06Lt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd18n06l, NTDV18N06L http://onsemi.com 3 0 0.06 30 20 0.04 0.02 0 10 0.1 0.12 40 0.08 2 1.6 1.2 1.4 1 0.8 0.6 1 1000 10000 04 20 2 1 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.06 30 20 0.04 0.02 0 10 figure 3. on ? resistance versus gate ? to ? source voltage i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 40 ? 50 50 25 0 ? 25 75 125 100 1.6 2.4 5.6 040 30 20 60 10 3 10 30 8 v v ds 10 v t j = 25 c t j = ? 55 c t j = 100 c t j = 100 c v gs = 5 v v gs = 10 v 150 175 v gs = 0 v i d = 9 a v gs = 5 v 0.1 0.12 v gs = 10 v t j = 25 c t j = ? 55 c t j = 100 c 40 t j = 150 c t j = 100 c 20 0 40 10 30 3.2 4 t j = 25 c t j = ? 55 c 50 100 6 v 5 v 4.5 v 4 v 3.5 v 3 v 1.8 5.5 v 4.8 0.08 10
ntd18n06l, NTDV18N06L http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is af fected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. c rss 10 0 10 15 20 25 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 1400 400 0 v gs v ds 600 200 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 800 1000 1200
ntd18n06l, NTDV18N06L http://onsemi.com 5 20 0 0.6 drain ? to ? source diode characteristics v sd , source ? to ? drain voltage (volts) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( ) 1 10 100 1000 1 t, time (ns) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current v gs , gate ? to ? source voltage (volts) 0 6 4 0 q g , total gate charge (nc) 8 2 6 100 24 12 0.68 0.76 1 4 8 12 i d = 18 a t j = 25 c v gs q 2 q 1 q t t r t d(off) t d(on) t f 10 v ds = 30 v i d = 18 a v gs = 5 v 0.84 0.92 8 16 10 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. although many e ? fets can withstand the stress of drain ? to ? source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntd18n06l, NTDV18N06L http://onsemi.com 6 safe operating area figure 11. maximum rated forward biased safe operating area t j , starting junction temperature ( c) e as , single pulse drain ? to ? source figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 100 v ds , drain ? to ? source voltage (volts) figure 13. thermal response 1 100 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 0 25 50 75 100 125 i d = 12 a 10 10 175 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 20 40 80 v gs = 15 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s 150 60 r(t), effective transient thermal resistance (normalized) t, time ( s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e-01 1.0e-02 1.0e-03 1.0e-04 1.0e-05
ntd18n06l, NTDV18N06L http://onsemi.com 7 package dimensions dpak (single gauge) case 369c ? 01 issue d style 2: pin 1. gate 2. drain 3. source 4. drain b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw
ntd18n06l, NTDV18N06L http://onsemi.com 8 package dimensions 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d ? 01 issue c style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ntd18n06l/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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